Random progress from days 2 and 3 of innovation week.


Learned of Lava; eager to find out how much easier it is to do circuit design in a Haskell DSL.

Complaining a lot that Verilog is too verbose. For example, if-then-else in Verilog:

if <pred> begin <stmt>; end else begin <stmt>; end

I'm told I shouldn't complain because VHDL is much worse. Also, the implicit type coersions make me nervous, e.g. you can add a reg [7:0] to a 3'b011 no problem, no complaint. If you're not familiar with Verilog, that's an 8-bit register added to a 3-bit binary literal.

Just for the fun of it, here's a standard pulse width modulator (pwm) I wrote. The module is pretty simple, using a clock signal, some flip-flops, an adder, and a comparator. Here's the Verilog code:

module pwm #(parameter CTR_SIZE = 8) (
   input clk,
   input rst,
   input [CTR_SIZE-1:0] compare,
   output pwm

reg pwm_d, pwm_q;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;

assign pwm = pwm_q;

always@(*) begin
    ctr_d = ctr_q + 1'b1;
   if (compare > ctr_d) begin
       pwm_d = 1'b0;
    end else begin
        pwm_d = 1'b1;

always@(posedge clk) begin
    if (rst) begin
       ctr_q <= 1'b0;
   end else begin
       ctr_q <= ctr_d;

   pwm_q <= pwm_d;


Design tools

Having fun with FPGA design tools. They are astonishingly complicated. To compile and synthesize a circuit which blinks a single LED the (~17 GB) tool chain generates:

  • 120 files
  • 43 of which are called . (that is a lot of extensions!)
  • 33 of which are files with .exe extensions (this is on Linux)

The tools come with lots of bells, whistles, and pretty pictures though. Here is a circuit diagram for a simple pulse width modulator I wrote:

PWM Circuit Diagram

Running the circuit in a test bench simulation you can see the digital signals over time (a 20 microsecond window in this case):

PWM Test Bench

Analog world

But life isn't all digital. I'd like to hear some signals with my ears eventually. So I spent part of the afternoon building an 8-bit DAC to sit in between my FPGA and a little speaker I scrounged from a clock radio. The DAC consists of a ladder of resistors that compute a weighted sum of 8 digital signals as it's output voltage. There's also an OpAmp at the end to buffer the ladder-side circuit from the speaker-side circuit. It's the IC at the end of the breadboard in this picture:

8 bit DAC

Here is the whole setup, FPGA, 8-bit DAC, and speaker:

FPGA + DAC + Speaker


Tomorrow's plan is:

  • finish the four waveform generators (square, pulse, triangle, sawtooth)
  • figure out how I want to get parameters (frequency, amplitude, enable, logical combination) to the generators
  • test the things end-to-end
  • (stretch) implement filters


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