Innovation Week 2, Part 2

Random progress from days 2 and 3 of innovation week.


Learned of Lava; eager to find out how much easier it is to do circuit design in a Haskell DSL.

Complaining a lot that Verilog is too verbose. For example, if-then-else in Verilog:

if <pred> begin <stmt>; end else ...
more ...