Innovation Week 2, Part 2

Random progress from days 2 and 3 of innovation week.

Languages

Learned of Lava; eager to find out how much easier it is to do circuit design in a Haskell DSL.

Complaining a lot that Verilog is too verbose. For example, if-then-else in Verilog:

if <pred> begin <stmt>; end else ...
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Innovation Week 2

It's innovation week again at work. That means I have all week to do whatever the heck I want as long as it is fun, interesting, and results in something to show off at the end of the week.

Xilinx Spartan FPGA

This year my goal is to learn something about programming ...

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